The present invention relates generally to field effect transistors of integrated circuits, and more particularly, to a vertical field effect transistor with metal oxide as a sidewall gate insulator for a double-gate or a surrounded gate structure.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension junction 104 and a source extension junction 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension junction 104 and the source extension junction 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate structure 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate structure 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate structure 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate structure 118 and the gate dielectric 116.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET 100 are scaled down further, such as tens of nanometers for the gate length of the MOSFET 100 for example, the MOSFET 100 exhibits disadvantageous short channel effects, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, scaling down the dimensions of the MOSFET 100 with the drain extension junction 104, the drain contact junction 108, the source extension junction 106, and the source contact junction 112 fabricated laterally within the semiconductor substrate 102 may be limited by such short channel effects, as known to one of ordinary skill in the art of integrated circuit fabrication.
Nevertheless, a MOSFET that occupies less area of the semiconductor substrate 102 is desired for fabrication of more compact integrated circuits. In addition, minimization of short channel effects is desired as the dimensions of the MOSFET are scaled down further. Thus, a novel MOSFET structure that occupies less area of the semiconductor substrate with minimized short channel effects is desired.
Accordingly, in a general aspect of the present invention, a vertical field effect transistor is fabricated to have a double gate structure or a surrounded gate structure for minimizing short channel effects in the vertical field effect transistor.
In one embodiment of the present invention, for fabricating a vertical field effect transistor on a semiconductor substrate, a first layer of dielectric material is deposited on the semiconductor substrate. A layer of metal is then deposited on the first layer of dielectric material, and a second layer of dielectric material is deposited on the layer of metal. A channel opening is etched through the second layer of dielectric material, the layer of metal, and the first layer of dielectric material. A source and drain dopant is implanted through the channel opening and into the semiconductor substrate to form a drain region of the vertical field effect transistor in the semiconductor substrate. Metal oxide is then formed at any exposed surface of the layer of metal on sidewalls of the channel opening in a thermal oxidation process, and the metal oxide is a gate dielectric of the vertical field effect transistor.
The channel opening is filled with a semiconductor material by epitaxially growing the semiconductor material from the semiconductor substrate at a bottom wall of the channel opening. A semiconductor structure is also grown from the semiconductor material filling the channel opening, and the semiconductor structure extends above the channel opening.
The source and drain dopant is also implanted into the semiconductor structure to form a source region of the vertical field effect transistor. A thermal anneal is performed such that the drain region extends into the channel opening to be between the metal oxide at the sidewalls of the channel opening and such that the source region extends into the channel opening to be between the metal oxide at the sidewalls of the channel opening. A portion of the semiconductor material in the channel opening remains undoped without the source and drain dopant between the drain region and the source region to form a channel region of the vertical field effect transistor.
The present invention may be used to particular advantage when the first layer of dielectric material and the second layer of dielectric material are comprised of silicon dioxide having a thickness in a range of from about 300 xc3x85 to about 500 xc3x85, when the layer of metal is comprised of one of aluminum, titanium, or tantalum having a thickness in a range of from about 200 xc3x85 to about 1000 xc3x85, and when the metal oxide is comprised of one of aluminum oxide (Al2O3), titanium oxide (TiO2), and tantalum oxide (Ta2O5).
In this manner, because the drain region, the channel region, and the source region of the vertical field effect transistor are formed vertically upward from the semiconductor substrate, the field effect transistor may occupy less space of the semiconductor substrate than the conventional lateral field effect transistor of the prior art. In addition, because the gate of the vertical field effect transistor is formed at a plurality of sidewalls of the channel opening, short channel effects of the vertical field effect transistor may be further controlled and prevented.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.